And I think that's the most immediate constraint on not going wider. So going superscalar means substantially increasing the bandwidth of that cache, which is surely not trivial (at least not if you care about limiting energy). Looking forward to what they will cook up! At any rate, there is a lot of potential here and they seem to be designing their things in a way that will allow them bigger advancements later.Ĭlick to expand.Yes, I didn't want to get into this, but one reason going superscalar in this way is not completely trivial, is reading registers.Īpple, like everyone, uses a register cache to hold "active" registers and avoid the delay and energy cost of reading from SRAM each time, but Apple's scheme seems to be more aggressive than anyone else's (can hold destination registers, not just source registers more sophisticated compiler controls for suggesting that certain registers are high priority for retention, vs no longer of interest and the ability to indicate in an instruction the prefetching into the register cache of a register to be used a few cycles later. And maybe three-way superscalar with three symmetrical pipelines will also be possible in the future. But say they make the FP pipelines more flexible so that both can do FP32/16 - then they can double the peak FP throughput for only a minor increase in area (all the other machinery is still in place). Right now they seem to have separate FP32, FP16, and INT pipelines. The beauty of this is that it opens up Apple for Nvidia-style expansion of pipeline functionality. I do wonder what this means for the operand bandwidth and data path contention, one needs a fairly wide bus to sustain two 32-wide SIMD pipelines simultaneously. By the way, is this the first time that a SIMT GPU is doing really superscalar execution with two instruction from two programs decoded and dispatched per cycle? To my knowledge, until now only Nvidia did something like that, but they still dispatch one SIMD per cycle (and alternate between two SIMDs).
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